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ADP4000 Product Preview Programmable Multi- Phase Synchronous Buck Converter with PMBus
The ADP4000 is an integrated power control IC with a PMBus interface. The ADP4000 can be programmed for 1-, 2-, 3-, 4-, 5- or 6phase operation, allowing for the construction of up to six complementary buck switching stages. The ADP4000 supports PSI, which is a power state indicator and can be used to reduce number of operating phases at light loads. The ADP4000 includes a PMBus interface, which can be used to program system set points such as voltage offset, load line, phase balance and output voltage. Key system performance data such as CPU current, CPU voltage, and power and fault conditions can also be read back over the PMBus from the ADP4000.
Features http://onsemi.com MARKING DIAGRAM
ADP4000 JCPZ #YYWW XXXXX CCCCC LFCSP40 CASE 932AD
* * * * * * * * * * *
PMBus Interface Supports Both VR11 and VR11.1 Specifications Digitally Programmable 0.375 V to 1.6 V Output Additional 200 mV Offset Programmable (Max 1.8 V Output) Selectable 1-, 2-, 3-, 4-, 5-, or 6-Phase Operation Fast-Enhanced PWM FlexModet TRDET to Improve Load Release Active Current Balancing Between All Output Phases Supports On-The-Fly (OTF) VID Code Changes Supports PSI - Power Saving Mode This is a Pb-Free Device
xx # YYWW XXX CCC
= Device Code = Pb--Free Package = Date Code = Assembly Lot = Country of Origin
PIN ASSIGNMENT
VCC3 PWRGD PSI VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VCC 48 47 46 45 44 43 42 41 40 39 38 37
Typical Applications
* Servers * Desktop PC's * POLs (Memory)
ALERT FAULT SDA SCL EN GND ADD / VSENSE2 VSENSE1 IMON TTSENSE VRHOT IREF
1 2 3 4 5 6 7 8 9 10 11 12
PIN 1 INDICATOR
ADP4000
TOP VIEW (Not to Scale)
36 35 34 33 32 31 30 29 28 27 26 25
PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 SW1 SW2 SW3 SW4 SW5 SW6
ORDERING INFORMATION
Device* Package Shipping
ADP4000JCPZ--REEL LFCSP48 2500/Tape & Reel ADP4000JCPZ--RL7 LFCSP48 750/Tape & Reel
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
*The "Z' suffix indicates Pb--Free package. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: ADP4000/D
(c) Semiconductor Components Industries, LLC, 2008
June, 2008 - Rev. P0 -
1
RT 13 RAMPADJ 14 TRDET 15 FBRTN 16 COMP 17 FB 18 CSREF 19 CSSUM 20 CSCOMP 21 ILIMFS 22 ODN 23 OD1 24
ADP4000
ADD SCL
7 4
SDA TRDET RT
3 15 13
RAMPADJ
14
VCC
37
VCC3
48
ALERT 1 COMPARATOR FAULT 2
LIMIT REGISTERS
PMBUS
SHUNT REGULATOR
3.3 V REGULATOR
23
ODN
STATUS REGISTERS GND 6 EN/VTT 5 850 mV
- +
UVLO SHUTDOWN
OSCILLATOR DIGITAL CONFIG & VALUE CONTROL REGISTERS
24 + - + -
OD1
SET RESET
EN
36
CMP
PWM1
CMP
RESET
35
PWM2
VSENSE1 8
MUX
ADC CURRENT BALANCING CIRCUIT
+ -
CMP
RESET
2 / 3 / 4 /5 / 6 PHASE DRIVER LOGIC
34
PWM3
VRHOT 11 TTSENSE 10 Over Voltage Threshold CSREF
THERMAL THROTTLING CONTROL
+
CONTROL
-
CMP
RESET
33
PWM4
+ -
32
CMP
RESET
31
PWM5
- + + -
PWM6
CMP
RESET CURRENT LIMIT
Under Voltage Threshold
+ -
CROWBAR
30 29 28
SW1 SW2 SW3 SW4 SW5 SW6
PWRGD 47
DELAY
27 26 25
CONTROL
+ + - + -
21 19 20
CSCOMP CSREF CSSUM IMON
ILIMFS 22
IREF 12 COMP 17
CONTROL
18
ADP4000
PSI 46 PRECISION REFERENCE
CONTROL
VID DAC
BOOT VOLTAGE& SOFT- START CONTROL -
16
45
44
43
42
41
40
39
38
FBRTN
VID0 VID1 VID2 VID3 VID4 VID5
VID6 VID7
Figure 1. Block Diagram
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2
-
CURRENT MEASUREMENT AND LIMIT
9
FB
- +
2.2
Vin 12 V
18 nF
4.7 uF
ADP3121 10 nF
1200 uF 16 V 1
BST 150 nH
Vcc Core
DRVH 8 SW 7 PGND 6 DRVL 5 10
Vcc Core (RTN)
2
IN OD VCC
3 4
4.7 uF 2.2 4.7 uF 18 nF
Vcc Sense Vss Sense
ADP3121 10 nF
1k 2 1
BST 150 nH IN OD VCC 2.2 18 nF 4.7 uF DRVL 5 PGND 6 10 SW 7
DRVH 8
1 uF X7R 680 4 680
3
4.7 uF
PSI POWER GOOD 1 uF X7R
ADP3121
1
10 nF 150 nH
PSI
VCC
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VCC3
PWRGD
ALERT ALERT PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 SW1 SW2 SW3 SW4 SW5 SW6 OD1 1k 1k 1 2 3 4 1k 1k 1k 1k 4 3 2 FAULT SDA SCL EN GND ADD/VSENSE2 VSENSE1 IMON PROCHOT VRHOT IREF FB ODN COMP ILIMFS RT 121 k 63.4 k 63.4 k 63.4 k 63.4 k 63.4 k 63.4 k CSSUM CSREF TRDET FBRTN RAMPADJ CSCOMP TTSENSE FAULT PMBus Interface
BST IN OD VCC 2.2 18 nF DRVL 5 PGND 6 SW 7
DRVH 8
6.8 k 1 nF
VTT I/O
4.7 uF
10
ADP4000
1k
4.7 uF
4.54 k
4.7 uF
ADP4000
Figure 2. Application Schematic
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ADP3121
BST IN OD VCC 4.7 uF 2.2
1500 pF X7R 69.8 k 35.7 k 100 k Thermistor 5% 82.5 k 4.99 k 6.81 k, 1% 348 k 560 pF 220 k 1500 pF X7R
3
3.3 pF 32.4 k 470 pF X7R
10 nF DRVH 8 SW 7 PGND 6 DRVL 5 10 18 nF 4.7 uF 150 nH
100 k NTC
20 k
0.1uF
ADP3121 10 nF
1 2 3 4
470 pF X7R
BST IN OD VCC 4.7 uF 2.2
DRVH 8 SW 7 PGND 6 DRVL 5
150 nH
1.21 k
10 18 nF 4.7 uF
ADP3121 10 nF
1 2 3 1000 pF 4
BST IN OD VCC 4.7 uF
DRVH 8 SW 7 PGND 6 DRVL 5
150 nH
10
ADP4000
ABSOLUTE MAXIMUM RATINGS
Rating Input Voltage Range (Note 1) FBRTN PWM2 to PWM6, Rampadj SW1 to SW6 SW1 to SW6 (<200 ns|) All other Inputs and Outputs Storage Temperature Range Operating Ambient Temperature Range ESD Capability, Human Body Model (Note 2) ESD Capability, Machine Model (Note 2) Moisture Sensitivity Level Lead Temperature Soldering Reflow (SMD Styles Only), Pb--Free Versions (Note 3) ESDHBM ESDMM MSL TSLD TSTG Symbol VIN VFBRTN Value --0.3 to 6 --0.3 to + 0.3 V --0.3 to VIN + 0.3 --5 to +25 V --10 to +25 V --0.3 to VIN + 0.3 --65 to 150 0 to 85 2 100 3 260 Unit V V V V V V C C kV V -C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to Electrical Characteristics and Application Information for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC--Q100--002 (EIA/JESD22--A114) ESD Machine Model tested per AEC--Q100--003 (EIA/JESD22--A115) Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78 3. For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS
Characteristic Thermal Characteristics, LFCSP, 7 mm * 7 mm (Note 1) Thermal Resistance, Junction--to--Air (Note 4) Thermal Resistance, Junction--to--Lead 2 (Note 4) Symbol RJA RJL Value 24 10 Unit C/W
4. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.
OPERATING RANGES (Note 1)
Characteristic Output Voltage (Adjustable Version Only) (Note 5) Ambient Temperature 5. Maximum limit for VOUT = VOUT(NOM) -- 10%. Symbol VOUT TA Min 0.375 0 Max 1.8 85 Unit V C
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ADP4000
PIN ASSIGNMENT
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Pin Name ALERT FAULT SDA SCL EN GND ADD/ VSENSE2 VSENSE1 IMON TTSENSE VRHOT IREF RT RAMPADJ TRDET FBRTN COMP FB CSREF Description ALERT Output. Open drain output that asserts low when the VR exceeds a programmable limit. FAULT Output. Open drain output that asserts low when a fault has occurred. This fault can be due to VR or current--limit, crowbar, or undervoltage. The trip points are loaded into registers. Digital Input Output. PMBus serial data bi--directional pin. Requires PMBus pullup. Digital Input. PMBus serial bus clock open drain input. Requires PMBus pullup. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. PMBus Address Input. Connect a resistor to ground to select one of 8 addresses. This input is reconfigured after startup as an analog voltage monitor, VSENSE2. Analog Input. Measures an input voltage between 0 and 2.0 V and reports this back over the PMBus interface. Total Current Output Pin. VR Temperature Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the temperature at the desired thermal monitoring point. VR HOT Output. Open drain output that signals when the temperature at the monitoring point connected to TTSENSE exceeds the VRHOT temperature threshold. Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IILIMFS, and ITH(X). Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Transient Detect. This output is asserted low whenever a load release is detected Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Error Amplifier Output and Compensation Point. Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no load offset point. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the Power--Good and crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the current sense amplifier and the positioning loop response time. Current Sense and Limit Scaling Pin. An external resistor from this pin to CSCOMP sets the internal current sensing signal for current--limit and IMON. This value can be over--written using PMBus interface. Output Disable Logic Output for PSI operation. This pin is actively pulled low when PSI is low, otherwise it functions in the same way as OD1. Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to signal to the Driver IC that the driver high--side and low--side outputs should go low. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. Logic--Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3121. Connecting PWM6 to VCC disables PWM6, connecting PWM5 to VCC disables PWM5 and PWM6, etc. This means the ADP4000 can be setup to operate as a 1-- 2--, 3--, 4--, 5--, or 6--phase controller. Supply Voltage for the Device. A 340 resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5.0 V. Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.375 V to 1.6 V. Power State Indicator. Pulling this pin low places the controller in lower power state operation. Power--Good Output. Open--drain output that signals when the output voltage is outside of the proper operating range. 3.3 V Power Supply Output. A capacitor from this pin to ground provided decoupling for the interval 3.3 V LDO.
20 21 22 23 24 25 to 30 31 to 36
CSSUM CSCOMP ILIMFS ODN OD1 SW6 to SW1 PWM6 to PWM1 VCC VID7 to VID0 PSI PWRGD VCC3
37 38 to 45 46 47 48
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ADP4000
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN -- GND, for typical values TA = 25C, for min/max values TA = 0C to 85C; unless otherwise noted. (Notes 6 and 7) Parameter Reference Current Reference Bias Voltage Reference Bias Current Error Amplifier Output Voltage Range Accuracy Relative to nominal DAC output, referenced to FBRTN (see Figure 2) In startup VCOMP VFB VFB(BOOT) 0 --7 1.093 --77 --350 0 --1.0 IFB VR Offset Register = 111111, VID = 1.0 V VR Offset Register = 011111, VID = 1.0 V IFBRTN FB forced to VOUT --3% COMP = FB COMP = FB Internal Timer VID(X) VID(X) VID code change to FB change VID code change to PWM going low tBOOT VIL(VID) VIH(VID) IIN(VID) 200 5.0 0.8 --5.0 ICOMP GBW(ERR) 14.2 16 --193.75 193.75 100 500 20 25 2.0 0.3 200 1.1 --80 4.4 +7 1.107 --83 0 100 +1.0 17.7 V mV V mV mV % LSB mA mV mA mA MHz V/ms ms V V mA ns ms RIREF = 121 k VIREF IIREF 1.75 1.8 15 1.85 V mA Test Conditions Symbol Min Typ Max Unit
Load Line Positioning Accuracy Load Line Range Load Line Attenuation Differential Non--linearity Input Bias Current Offset Accuracy FBRTN Current Output Current Gain Bandwidth Product Slew Rate BOOT Voltage Hold Time VID Inputs Input Low Voltage Input High Voltage Input Current VID Transition Delay Time No CPU Detection Turn--Off Delay Time Oscillator Frequency Range Frequency Variation TA = 25C, RT = 270 k, 6--phase TA = 25C, RT = 130 k, 6--phase TA = 25C, RT = 68 k, 6--phase RT = 500 k to GND RAMPADJ -- FB, VFB = 1.0 V, IRAMPADJ = --150 mA fOSC fPHASE
0.25 225 245 500 850 2.03
9.0 265
MHz kHz
Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range Current Sense Amplifier Offset Voltage Input Bias Current, CSREF Input Bias Current, CSSUM Gain Bandwidth Product Current Sense Amplifier Slew Rate Input Common--Mode Range Output Voltage Range Output Current Current--Limit Latchoff Delay Time
VRT VRAMPADJ IRAMPADJ
1.93 --50 5.0 --1.0 --20 --10
2.13 +50 60 +1.0 +20 +10
V mV mA mV mA nA MHz V/ms
CSSUM -- CSREF (see Figure 4) CSREF = 1.0 V CSREF = 1.0 V CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF
VOS(CSA) IBIAS(CSREF) IBIAS(CSSUM) GBW(CSA)
10 10 0 0.05 3.0 3.0 500 8.0
V V mA ms
ICSCOMP Internal Timer
6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area. 7. Guaranteed by design, not production tested.
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ADP4000
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN -- GND, for typical values TA = 25C, for min/max values TA = 0C to 85C; unless otherwise noted. (Notes 6 and 7) Parameter PSI Input Low Voltage Input High Voltage Input Current Assertion Timing Deassertion Timing TRDET Output Low Voltage IMON Clamp Voltage Accuracy Output Current Offset Current-Limit Comparator ILIM Bias Current Current--Limit Threshold Current Current Balance Amplifier Common--Mode Range Input Resistance Input Current Input Current Matching Phase Balance Adjustment Range Low Phase Balance Adjustment Range High Delay Timer Internal Timer Timer Range Low Timer Range High Soft-Start Internal Timer Timer Range Low Timer Range High Enable Input Input Low Voltage Input High Voltage Input Current Delay Time ODN and OD1 Outputs Output Low Voltage Output High Voltage ODN / OD1 Pulldown Resistor 6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area. 7. Guaranteed by design, not production tested. IOD(SINK) = --400 mA IOD(SOURCE) = 400 mA VOL(ODN/1) VOL(ODN/1) 4.0 160 5.0 60 500 mV V k EN > 0.8 V, Internal Delay VIL(EN) VIH(EN) IIN(EN) tDELAY(EN) 0.8 --1.0 2.0 0.3 V V mA ms Soft--Start Slope Register = 010 Soft--Start Slope Register = 000 Soft--Start Slope Register = 111 0.5 0.1 1.5 V/ms V/ms V/ms Delay Time Register = 011 Delay Time Register = 000 Delay Time Register = 111 2.0 0.5 4.0 ms ms ms SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V Phase Bal Registers = 00000 Phase Bal Registers = 11111 VSW(X)CM RSW(X) ISW(X) ISW(X) --600 12 8.0 --6.0 --25 +25 18 12 +200 21 18 +6.0 mV k mA % % % CSREF -- CSCOMP)/RILIM, (CSREF -- CSCOMP) = 150 mV, RILIM = 7.5 k 4/3 x IIREF ILIM ICL 22 22 mA mA --5.5 10 x (CSREF -- CSCOMP)/RILIM 1.0 --3.0 1.15 3.0 800 5.5 V % mA mV IOUT = --6 mA VOL 150 300 mV Fsw = 300kHz Fsw = 300kHz 0.8 --5 3.3 825 0.3 V V mA ms ns Test Conditions Symbol Min Typ Max Unit
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ADP4000
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN -- GND, for typical values TA = 25C, for min/max values TA = 0C to 85C; unless otherwise noted. (Notes 6 and 7) Parameter Power-Good Comparator Undervoltage Threshold Undervoltage Adjustment Range Low Undervoltage Adjustment Range High Overvoltage Threshold Overvoltage Adjustment Range Low Overvoltage Adjustment Range High Output Low Voltage Power Good Delay Time During Soft--Start VID Code Changing VID Code Static Crowbar Trip Point Crowbar Adjustment Range Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM Outputs Output Low Voltage Output High Voltage PMBus Interface Logic High Input Voltage Logic Low Input Voltage Hysteresis SDA Output Low Voltage Input Current Input Capacitance Clock Frequency SCL Falling Edge to SDA Valid Time ALERT, FAULT Outputs Output Low Voltage Output High Leakage Current TTSENSE Inputs TTSENSE Voltage Range Source Current VRHOT Output Low Voltage Input Voltage Conversion Range ADC Resolution Analog / Digital Converter ADC Input Voltage Range ADC Resolution Total Unadjusted Error (TUE) Differential Non--linearity (DNL) 8 Bits 6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area. 7. Guaranteed by design, not production tested. 0 1.95 1.0 1.0 2.0 V mV % LSB LSB Weighting Internally Limited RIREF = 121 k IVRHOT(SINK) = --4mA 0 2.0 ITH 0 --110 --125 150 3.0 --140 300 2.0 V mA mV V mV IOUT = --6 mA VOH = 5.0 V VOL VOH 0.4 1.0 V mA ISDA = --6 mA VOL VIH; IIL CSCL, SDA fSCL --1 5.0 400 1.0 VIH(SDA,SCL) VIH(SDA,SCL) 500 0.4 1.0 2.1 0.8 V V mV V mA pF kHz ms IPWM(SINK) = --400 mA IPWM(SOURCE) = 400 mA VOL(PWM) VOH(PWM) 4.0 160 5.0 500 mV V Relative to DAC Output, PWRGD_Hi = 00 PWRGD_Hi Register Relative to FBRTN Overvoltage to PWM going low tCROWBAR 100 250 400 ms ns VCROWBAR 200 150 250 300 Internal Timer 100 2.0 250 200 300 400 300 350 ms ms ns mV mV mV Relative to Nominal DAC Output PWRGD_LO Register = 000 PWRGD_LO Register = 111 Relative to DAC Output, PWRGD_Hi = 00 PWRGD_Hi Register = 11 PWRGD_Hi Register = 00 IPWRGD(SINK) = --4 mA VOL(PWRGD) VPWRGD(OV) 200 VPWRGD(UV) --600 --500 --500 --150 300 150 300 150 300 400 --400 mV mV mV mV mV mV mV Test Conditions Symbol Min Typ Max Unit
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ADP4000
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN -- GND, for typical values TA = 25C, for min/max values TA = 0C to 85C; unless otherwise noted. (Notes 6 and 7) Parameter Analog / Digital Converter cont. Conversion Time, Voltage Channel Round Robin Cycle Time ADD Input ADD Output Current Address 000 Threshold Address 001 Threshold Address 010 Threshold Address 011 Threshold Address 100 Threshold Address 101 Threshold Address 110 Threshold Address 111 Threshold Supply VCC DC Supply Current (see Figure 2) UVLO Turn--On Current UVLO Threshold Voltage UVLO Turn--Off Voltage VCC3 Output Voltage VCC Rising VCC Falling IVCC3 = 1 mA VCC3 3.0 VUVLO 9.5 4.1 3.3 3.6 VCC VSYSTEM = 13.2 V, RSHUNT = 340 IVCC 4.7 5.25 20 6.5 5.75 25 11 V mA mA V V V 0.15 0.3 0.5 0.75 1.0 1.35 1.8 IADD = 2/3*IIREF IADD 10 0.1 0.225 0.45 0.675 0.9 1.25 1.7 mA V V V V V V V V Averaging Enabled (32 averages) 80 TBD ms ms Test Conditions Symbol Min Typ Max Unit
6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area. 7. Guaranteed by design, not production tested.
TYPICAL CHARACTERISTICS
3000
2500
2000
Frequency (Hz)
1500
PWM1
1000
500
0 13 20 30 43 50 68 75 82 130 180 270 395 430 500 680 850
RT (k)
Figure 3. ADP4000 RT vs Frequency
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ADP4000
TEST CIRCUITS
+12 V
8 BIT VID CODE
680 +1 m F
680
100 nF
PWRGD PSI VID0
NC NC NC +1.25 V NC EN
VCC3
GND PSI_SET LLSET IMON TTSENSE RAMPADJ TRDET FBRTN VRHOT IREF RT 121 k
ADP4000
VID6 VID7 VCC PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 SW1 SW2 SW3 SW4 SW5 SW6 ODN OD1 10 k
VID1 VID2 1 k
20 k
100 nF
Figure 4. Closed-Loop Output Voltage Accuracy
CSSUM CSCOMP ILIMITFS
COMP FB CSREF
VID3 VID4 VID5
12 V 12 V
ADP4000
680 VCC 37 COMP 17
ADP4000
680 VCC 37 CSCOMP 21
680
680
10 k
FB 18
39 k
100 nF CSSUM 20 CSREF 19 GND 6 VOS = CSCOMP - 1 V 40 1V 6 - CSREF 19 + GND
1 k
VID DAC
1V
VFB= FBV = 80mV - FB V = 0 mV
Figure 5. Current Sense Amplifier VOS
Figure 6. Positioning Voltage
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ADP4000
Description
The ADP4000 is a 6-Phase VR11.1 regulator with a PMBus Interface Typical application circuits is shown in Figure 2.
Startup Sequence
current-limit latchoff as explained in the Current-Limit section. The current-limit timer is set to 4 times the delay timer.
Table 1. Delay Codes
Code 000 001 010 011 100 101 110 111 Delay (msec) 0.5 1 1.5 2 = default 2.5 3 3.5 4
The ADP4000 follows the VR11 start-up sequence shown in Figure 7. After both the EN and UVLO conditions are met, a programmable internal timer goes through one delay cycle TD1. This delay cycle is programmed using Delay Command, default delay = 2 ms, see Table 1 for programmable values). The first six clock cycles of TD2 are blanked from the PWM outputs and used for phase detection as explained in the following section. Then the programmable internal soft-start ramp is enabled (TD2) and the output comes up to the boot voltage of 1.1V. The boot hold time is also set by Delay Command. This second delay cycle is called TD3. During TD3 the processor VID pins settle to the required VID code. When TD3 is over, the ADP4000 reads the VID inputs and soft-starts either up or down to the final VID voltage (TD4). After TD4 has been completed and the PWRGD masking time (equal to VID on the fly masking) is finished, a third cycle of the internal timer sets the PWRGD blanking (TD5). The internal delay and soft-start times are programmable using the serial interface and the Delay Command and the Soft-Start Commands.
5.0 V SUPPLY UVLO THRESHOLD
The delay timer is programmed using Bits <2:0> of the Ton Delay command (0xD4). The delay can be programmed between 0.5 msec and 4 msec. Table 1 provides the programmable delay times.
Soft-Start
VTT I/O (ADP4000 EN) VCC_CORE
0.85 V
TD3 VBOOT (1.1 V) VVID TD4 TD2
TD1
VR READY (ADP4000 PWRGD) 50 ms CPU VID INPUTS VID INVALID TD5 VID VALID
The soft-start slope for the output voltage is set by an internal timer. The default value is 0.5 V/msec, which can be programmed through the PMBus interface. After TD1 and the phase detection cycle have been completed, the SS time (TD2 in Figure 7) starts. The SS circuit uses the internal VID DAC to increase the output voltage in 6.25 mV steps up to the 1.1 V boot voltage. Once the SS circuit has reached the boot voltage, the boot voltage delay time (TD3) is started. The end of the boot voltage delay time signals the beginning of the second soft-start time (TD4). The SS voltage changes from the boot voltage to the programmed VID DAC voltage (either higher or lower) using 6.25 mV steps. The soft-start slew rate is programmed using Bits <2:0> of the Ton_Rise (0xD5) command code. Table 2 provides the soft-start values
Table 2. Slew Rate Codes
Code 000 001 010 011 100 101 110 111 Slew Rate (V/msec) 0.1 0.3 0.5 = default 0.7 0.9 1.1 1.3 1.5
Figure 7. System Startup Sequence for VR11 Internal Delay Timer
An internal timer sets the delay times for the startup sequence, TD1, TD3 and TD5. The default time is 2msec, which can be changed using the PMBus interface. This timer is used for multiple delay timings (TD1, TD3 and TD5) during the startup sequence. Also, it is used for timing the
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ADP4000
Master Clock Frequency
The clock frequency of the ADP4000 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 6. If 4 phases are in use then divide by 4.
RT = 1 - R TO n x f SW x Cr
(eq. 1)
where CT = 2.2 pF and RTO = 21 k
Output Voltage Differential Sensing
Figure 8. System Startup Sequence for VR11
Figure 8 shows typical startup waveforms for the ADP4000. Figure 8. Typical Start-up Waveforms Channel 1: CSREF (yellow) Channel 2: PWM1 (blue) Channel 3 : Enable (pink)
Phase Detection
During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP4000 operates as a 6-phase PWM controller. To operate as a 5-Phase Controller connect PWM6 to VCC. To operate as a 4-Phase Controller connect PWM5 and PWM6 to VCC. To operate as a 3-Phase Controller connect PWM4, PWM5 and PWM6 to VCC. To operate as a 2-Phase Controller connect PWM3, PWM4, PWM5 and PWM6 to VCC. To operate as a single-phase controller connect PMW2, PWM3, PWM4, PWM5 and PWM6 to VCC. Prior to soft-start, while EN is high the PWM6, PWM5, PWM4 PWM3 and PWM2 pins sink approximately 100 mA each. An internal comparator checks each pin's voltage vs. a threshold of 3.0 V. If the pin is tied to VCC, it is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold. PWM1 is low during the phase detection interval that occurs during the first six clock cycles of TD2. After this time, if the remaining PWM outputs are not pulled to VCC, the 100 mA current sink is removed, and they function as normal PWM outputs. If they are pulled to VCC, the 100 mA current source is removed, and the outputs are put into a high impedance state. The PWM outputs are logic-level devices intended for driving fast response external gate drivers such as the ADP3121. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be on at the same time to allow overlapping phases.
The ADP4000 combines differential sensing with a high accuracy VID DAC and reference, and a low offset error amplifier. This maintains a worst-case specification of 7 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and FBRTN pin. FB is connected through a resistor, RB, to the regulation point, usually the remote sense pin of the microprocessor. FBRTN is connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 100 mA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage.
Output Current Sensing
The ADP4000 provides a dedicated current-sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current, for the IMON output and for current-limit detection. Sensing the load current at the output gives the total real time current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side MOSFET. This amplifier can be configured several ways, depending on the objectives of the system, as follows: * Output inductor DCR sensing without a thermistor for lowest cost. * Output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature. * Sense resistors for highest accuracy measurements. The positive input of the CSA is connected to the CSREF pin, which is connected to the average output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors, to the inverting input CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor. This difference signal is used internally to offset the VID DAC for voltage positioning. This difference signal can be adjusted between 50% and 150% of the external value
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ADP4000
using the PMBus Loadline Calibration (0xDE) and Loadline Set (0xDF) commands. The difference between CSREF and CSCOMP is used as a differential input for the current-limit comparator. To provide the best accuracy for sensing current, the CSA is designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors to make it extremely accurate. The CPU current can also be monitored over the PMBus. The current-limit and the load line can be adjusted from the circuit component values over the PMBus.
Current-Limit Setpoint Table 3. Current-Limit
Code 0 0000 0 0001 1 0000 1 0001 1 1110 1 1111 Current-Limit (% of external limit) 50% 53.3% 100% = default 103.3% 143.3% 146.7%
Current-Limit, Short Circuit and latchoff protection
The current-limit threshold on the ADP4000 is programmed by a resistor between the ILIMFS pin and the CSCOMP pin. The ILIMFS current, IILIMFS, is compared with an internal current reference of 22 mA. If IILIMFS exceeds 22 mA then the output current has exceeded the limit and the current-limit protection is tripped. Where VILIMFS = VCSREF
I ILIMFS = V ILIMFS - V CSCOMP R ILIMFS R CS x R L x I LOAD R PH
(eq. 2)
V CSREF - V CSCOMP =
(eq. 3)
Where RL = DCR of the Inductor. Assuming that
R CS x R L = 1 m R PH
(eq. 4)
i.e. the external circuit is set up for a 1m Loadline then the RILIMFS is calculated as follows
I ILIMFS = 1 m x I LOAD R ILIMITFS
(eq. 5)
If the current-limit is reached and TD5 has completed, an internal latch-off delay time will start, and the controller will shut down if the fault is not removed. This delay is four times longer than the delay time during the startup sequence. The current-limit delay time only starts after the TD5 has completed. If there is a current-limit during start-up, the ADP4000 will go through TD1 to TD5, and then start the latchoff time. Because the controller continues to cycle the phases during the latchoff delay time, if the short is removed before the timer is complete, the controller can return to normal operation. The latchoff function can be reset by either removing and reapplying the supply voltage to the ADP4000, or by toggling the EN pin low for a short time. During startup when the output voltage is below 200 mV, a secondary current-limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current-limit limits the internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. Typical over-current latchoff waveforms are shown in Figure 9.
Assuming we want a current-limit of 150A that means that ILIMFS must equal 22 mA at that load.
20 mA = 1 m x 150 AD = 6.8 k R ILIMITFS
(eq. 6)
Solving this equation for RLIMITFS we get 6.8 k. The closest 1% resistor value is 6.8 k. The current-limit threshold can be modified from the resistor programmed value by using the PMBus interface using Bits <4:0> of the Current-Limit Threshold command (0xE2). The limit is programmable between 50% of the external limit and 146.7% of the external limit. The resolution is 3.3%. Table 3 gives some examples codes.
Figure 9. Overcurrent Latchoff Waveforms Channel 1: CSREF, Channel 2: COMP, Channel 3: PWM1
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An inherent per phase current-limit protects individual phases if one or more phases stops functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage.
Output Current Monitor Load Line Setting
IMON is an analog output from the ADP4000 representing the total current being delivered to the load. It outputs an accurate current that is directly proportional to the current set by the ILIMFS resistor.
I IMON = 10 x I ILIMFS
(eq. 7)
The Loadline is programmable over the PMBus on the ADP4000. It is programmed using the Loadline Calibration (0xDE) and Loadline Set (0xDF) commands. The loadline can be adjusted between 0% and 100% of the external RCSA. In this example RCSA = 1 m. RO needs to 0.8 m. Therefore programming the Loadline Calibration + Loadline Set Register to give a combined percentage of 80% will set the RO to 0.8 m.
Table 4. Loadline Commands
Code 0 0000 0 0001 1 0000 1 0001 1 1110 1 1111 Loadline (as a percentage of RCSA) 0% 3.3% 50% = default 53.3% 96.7% 100%
The current is then run through a parallel RC connected from the IMON pin to the FBRTN pin to generate an accurately scaled and filtered voltage as per the VR11.1 specification. The size of the resistor is used to set the IMON scaling. The scaling is set such that IMON = 900mV at the TDC current of the processor. This means that the RIMON resistor should be chosen as follows. From the Current-Limit Setpoint paragraph we know the following:
I ILIMFS = 1 m x I LOAD R ILIMFS 1 m x ILOAD R ILIMFS
(eq. 8)
Current Control Mode and Thermal Balance
I IMON = 10 x
(eq. 9)
For a 150 A current-limit RLIMFS = 7.5 k. Assuming the TDC = 135 A then VMON should equal 900 mV when ILOAD = 135 A. When ILOAD = 135A, IMON equals
I IMON = 10 x 1 m x 135 A = 198 mA 6.81 k
(eq. 10) (eq. 11)
V IMON = 900 mV = 198 mA x R MON
This gives a value of 4.54 k for RMON. If the TDC and OCP limit for the processor have to be changed then it may be necessary to change the ILIMITFS resistor only. This is because the ILIMITFS resistor sets up both the current-limit and also the current out of the IMON pin, as explained earlier. The IMON pin also includes an active clamp to limit the IMON voltage to 1.15 V MAX while maintaining accuracy at 900 mV full scale.
Active Impedance Control Mode
The ADP4000 has individual inputs (SW1 to SW6) for each phase that are used for monitoring the current of each phase. This information is combined with an internal ramp to create a current balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning as described in the section. The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. The balance between the phases can be programmed using the PMBus Phase Bal SW(x) commands (0xE3 to 0xE8). This allows each phase to be adjusted if there is a difference in temperature due to layout and airflow considerations. The phase balance can be adjusted from a default gain of 5 (Bits 4:0 = 10000). The minimum gain programmable is 3.75 (Bits 4:0 = 00000) and the max gain is 6.25 (Bits 4:0 = 11111).
Voltage Control Mode
For controlling the dynamic output voltage droop as a function of output current, the CSA gain and load line programming can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This allows enhanced feed-forward response.
A high gain, high bandwidth, voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in VID Code Table. The VID code is set using the VID Input pins or it can be programmed over the PMBus using the VOUT_Command. By default, the ADP4000 outputs a voltage corresponding to the VID Inputs. To output a voltage following the VOUT_Command the user first needs to program the required VID Code. Then the VID_EN Bits need to be enabled. The following is the sequence:
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1. Program the required VID Code to the VOUT_Command code (0x21) 2. Set the VID_EN bit (Bit 3) in the VR Config 1 A (0xD2) and on the VR Config 1B (0xD3). This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with Resistor RB and is used for sensing and controlling the output voltage at this point. A current source (equal to IFB) from the FB pin flowing through RB is used for setting the no load offset voltage from the VID voltage. The no load voltage is negative with respect to the VID DAC for Intel CPU's. The value of RB can be found using the following equation.
RB = V VID - V ONL I IFB
(eq. 12)
The size of the internal ramp can be made larger or smaller. If it is made larger, stability and noise rejection improves but the transient performance decreases. If the ramp is made smaller then the transient response improves however noise rejection and stability degrades.
COMP Pin Ramp
There is a ramp signal on the COMP signal, which is due to the droop voltage and the output voltage ramps. This ramp adds to the internal ramp to produce the following ramp signal at the PWM input.
V RT =
1-
VR
2x(1-nxD) nxf SWxC XxR O
(eq. 15)
An offset voltage can be added to the control voltage over the serial interface. This is done using Bits <5:0> of the VOUT_TRIM (0xDB) and VOUT_CAL (0xDC) Commands. The max offset that can be applied is 193.75 mV (even if the sum of the offsets > 193.75mV). The LSB size is 6.25 mV. A positive offset is applied when Bit 5 = 0. A negative offset is applied when Bit 5 = 1.
Table 5. Offset Codes
VOUT_ TRIM CODE 00 1000 10 0001 00 1111 TRIM OFFSET VOLTAGE 50 mV -6.25 mV 93.75 mV VOUT_ CAL CODE 00 0010 10 1110 10 0001 CAL OFFSET VOLTAGE 12.5 mV -87.5 mV -6.25 mV TOTAL OFFSET VOLTAGE 62.5 mV -93.75 mV 87.5 mV
Where Cx = bulk capacitance RO = Droop n = number of phases fSW = switching frequency per phase D = duty cycle VR = Internal Ramp Voltage (calculated in Rampadj section of this data sheet) This ramp voltage should be set to at least 0.5 V for noise immunity reasons. If it is less than 0.5 V then decrease the ramp resistor.
Dynamic VID
RAMPADJ Input Current
The resistor connected to the Rampadj pin sets the internal PWM ramp. The value for this resistor is chosen to provide the combination of thermal balance, stability and transient response.
RR = AR x L 3 x A D x R DS x C R
(eq. 13)
Where AR is the internal ramp amplifier gain (= 0.5) AD is the current balancing amplifier gain (= 5) RDS is the total low side MOSFET on resistance CR is the internal ramp capacitor value (= 5pF). The internal ramp voltage can be calculated as follows:
VR = A R x (1 - D) x V VID R R x C R x fSW
(eq. 14)
The ADP4000 has the ability to respond to dynamically changing VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as Dynamic VID (DVID). A DVID can occur under either light or heavy load conditions. The processor signals the controller by changing the VID inputs (or by programming a new VOUT_Command) in a single or multiple steps from the start code to the finish code. This change can be positive or negative. When a VID bit changes state, the ADP4000 detects the change and ignores the DAC inputs for a minimum of 200 ns. This time prevents a false code due to logic skew while the VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 100 ms to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer. If a VID off code is detected the ADP4000 will wait for 5 msec to ensure that the code is correct before initiating a shutdown of the controller. The ADP4000 also uses the TON_Transition command code (0xD6) to limit the DVID slew rates. These can be encountered when the system does a large single VID step for power state changes, thus the DVID slew rate needs to be limited to prevent large inrush currents.
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The transition slew rate is programmed using Bits <2:0> of the Ton_Transition (0xD6) command code. Table 6 provides the soft-start values.
Table 6. Transition Rate Codes
Code 000 001 010 011 100 101 110 111 Transition Rate (V/msec) 1 3 = default 5 7 9 11 13 15
Power Good Monitoring
Enhanced Transients Mode
The ADP4000 incorporates enhanced transient response for both load step up and load release. For load step up it senses the output of the error amp to determine if a load step up has occurred and then sequences on the appropriate number of phases to ramp up the output current. For load release, it also senses the output of the error amp and uses the load release information to trigger the TRDET pin, which is then used to adjust the error amp feedback for optimal positioning. This is especially important during high frequency load steps. Additional information is used during load transients to ensure proper sequencing and balancing of phases during high frequency load steps as well as minimizing the stress on components such as the input filter and MOSFET's.
TRDET and Phase Shuffling
The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified in the specifications above based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if the VID DAC inputs are in no CPU mode, or whenever the EN pin is pulled low. PWRGD is blanked during a DVID event for a period of 100 ms to prevent false signals during the time the output is changing. The PWRGD circuitry also incorporates an initial turn-on delay time (TD5). Prior to the SS voltage reaching the programmed VID DAC voltage and the PWRGD masking time finishing, the PWRGD pin is held low. Once the SS circuit reaches the programmed DAC voltage, the internal timer operates. The default range for the PWRGD comparator is +300 mV and -500 mV. However these values can be adjusted over the PMBus. The high limit is programmed using Bits <1:0> of Command Code 0xE0 and the low limit is programmed using Bits <2:0> of Command code 0xE1. The following is a table of the programmable values.
Table 7. PWRGD High Limits
Code 00 01 10 11 PWRGD High Limits +300mV (default) +250 mV +200 mV +150 mV
The ADP4000 senses the error amp output and triggers the TRDET pin when a load release takes place. The TRDET circuit, as shown in Figure 2, adjusts the feedback for optimal positioning especially during high frequency load steps. TRDET is also used to trigger phase shuffling. If repeated transients take place at the switching frequency then its possible for one phase to carry most of the currrent. To prevent this from happening the ADP4000 will shuffle the phases whenever a load release happens, i.e. it will randomize the phase sequence.
Reference Current
Table 8. PWRGD Low Limits
Code 000 001 010 011 100 101 110 111 PWRGD Low Limits -500mV (default) -450 mV -400 mV -350 mV -300 mV -250 mV -200 mV -150 mV
The IREF pin is used to set an internal current reference. This reference current sets IFB and ITTSENSE. A resistor to ground programs the current based on the 1.8 V output.
I REF = 1.8 V R IREF
(eq. 16)
Power State Indicator
Typically, RIREF is set to 121 k to program IREF = 15 mA. The following currents are then equal to
I FB = 16 x I REF = 16 mA 15 I TTSENSE = - 8 (IREF) = - 120 mA
(eq. 17)
The PSI pin is an input used to determine the operating state of the load. If this input is pulled low, the load is in a low power state and the controller asserts the ODN pin low, which can be used to disable phases and maintain better efficiency at lighter loads. The sequencing into and out of low power operation is maintained to minimize output deviations as well as providing full power load transients immediately after exiting a low power state.
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The user can program how many phases are enabled when PSI is asserted. By default only phase 1 is enabled. The number of phases enabled can be changed over the PMBus. However extreme care should be taken to ensure that OD1 is connected to all phases enabled during PSI. The number of phases enabled during PSI is programmed using Bits 7 and 6 of the MFR Config Command (0xD1)
Table 9. # Phases Enabled During PSI
# of Phases Running Normally 6 Code # of Phases Running During PSI 1 2 3 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Phases Running 1 1 and 4 1, 3 and 5 1 1 1 and 4 1 1 1 1 and 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Output Enable and UVLO
00 01 10 11
5
00 01 10 11
For the ADP4000 to begin switching, the input supply current to the controller must be higher than the UVLO threshold and the EN pin must be higher than its 0.8 V threshold. This initiates a system startup sequence. If either UVLO or EN is less than their respective thresholds, the ADP4000 is disabled. This holds the PWM outputs at ground and forces PWRGD, ODN and OD1 signals low. In the application circuit (see Figure 2), the OD1 pin should be connected to the OD inputs of the external drivers for the phases that are always on. The ODN pin should be connected to the OD inputs of the external drivers on the phases that are shut down during low power operation. Grounding the driver OD inputs disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors.
Thermal Monitoring
4
00 01 10 11
3
00 01 10 11
2
00 01 10 11
1
00 01 10 11
The actual phases enabled depend upon how many phases are enabled for normal operation. For example if 4 phases are enabled normally and 2 during PSI, then Phase 1 and Phase 3 will be enabled during PSI.
Output Crowbar
As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 300 mV. The value for the crowbar limit follows the programmable PWRGD high limit. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current-limits the input supply or blows its fuse, protecting the microprocessor from being destroyed.
The ADP4000 includes a thermal monitoring channel using a thermistor. Temperature trip points can be set for ALERT and FAULT levels through the PMBus interface. Also, the temperature values can be read back over the PMBus interface. The VR thermal monitoring circuits require an NTC thermistor to be placed from TTSENSE to GND. For best accuracy, the thermistors can be linearized using resistors. A fixed current of 8 times IREF (normally giving 120 mA) is sourced out of the TTSENSE pin into the thermistor. When the TTSENSE temperature exceeds the OT Fault Limit (0x51), VRHOT is asserted. The temperature value is reported back in the Read_Temperature1 command. The AP4000 measures the voltage on the TTSENSE pin and calculates the temperature using the following formula: Read_Temperature_1 = (TTSENSE Voltage)*TTSENSE Gain + TTSENSE Offset. The TTSENSE Gain and Offset factors depend upon the combination of thermistor and linearizing register used in the circuit and can be programmed by the user using commands TTSENSE Gain (addr = 0xF7) and TTSENSE Offset (addr = 0xF8). The default values in the ADP4000 are for a 100 k Thermistor and a 20 k Linearizing resistor. If the user would like to measure the voltage directly then the TTSENSE Gain should be programmed to 1 and the Offset should be programmed to 0.
Voltage Monitoring
The ADP4000 can monitor up to three voltages. It can monitor the voltage on the EN pin and reports this back in a register. It can also monitor the voltage on the VSENSE1 and the VSENSE2 pins and report these back in registers over PMBus. The ADC range for the voltage measurements
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is 0 V to 2.0 V. Voltages greater than 2.0 V can monitored using a resistor divider network. Voltage measurements are 10 bits wide. Vsense1 is intended to measure the input voltage and report this back in the READ_VIN command. However the input voltage is typically 12 V and the ADC range is only 0 V to 2.0 V. Therefore an external resistor divided is needed, the ADP4000 assumes that an 8- resistor divider is used, the -1 ADP4000 measures the voltage on the pin and multiples by 8 and places the result in the Read Vin register. The circuit in Figure 2 uses a 6.8 K and a 1.0 k resistor to divide the input voltage by 8.
Shunt Resistor PMBus Interface
Control of the ADP4000 is carried out using the PMBus Interface. The physical protocol for PMBus closely matches that of SMBus. The ADP4000 is connected to this bus as a slave device, under the control of a master controller. To setup the PMBus Address the ADP4000 sources a 10 mA current from the ADD pin through an external resistor. The voltage is then measured by the ADC and user to set the PMBus address. The table below gives the thresholds for each possible PMBus address.
Table 10. Setting Up the PMBus Address
Address (8 Bits) 0xC0 0xC2 0xC4 0xC6 0xC8 0xCA 0xCC 0xCE High Threshold 0.1 0.225 0.45 0.675 0.9 1.25 1.7 -Low Threshold -0.15 0.3 0.5 0.75 1.0 1.35 1.8
The ADP4000 uses a shunt to generate 5.0 V from the 12 V supply range. A trade-off can be made between the power dissipated in the shunt resistor and the UVLO threshold. Figure 10 shows the typical resistor value needed to realize certain UVLO voltages. It also gives the maximum power dissipated in the shunt resistor for these UVLO voltages.
400 0.325 0.3 0.275 300 0.25 250 0.225 0.2 0.175 8 9 10 11 12 13 14 15 16 Rshunt Pshunt 2--0603 Limit 2--0805 Limit
350
200
150
ICC (UVLO)
Figure 10. Typical Shunt Resistor Value and Power Dissipation for Different UVLO Voltage
The maximum power dissipated is calculated using the Equation 18.
P MAX =
VIN(MAX) - VCC(MIN)
R SHUNT
2
(eq. 18)
where: VIN(MAX) is the maximum voltage from the 12 V input supply (if the 12 V input supply is 12 V 5%, VIN(MAX) = 12.6 V; if the 12 V input supply is 12 V 10%, VIN(MAX) = 13.2 V). VCC(MIN) is the minimum VCC voltage of the ADP4000. This is specified as 4.75 V. RSHUNT is the shunt resistor value. The CECC standard specification for power rating in surface-mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W.
Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low- -high -totransition when the clock is high might be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 1. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the tenth clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as No Acknowledge. The master takes the data line low during the low period before the tenth clock pulse, and then high during the tenth clock pulse to assert a stop condition. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the ADP4000, write operations contain one, two or three bytes, and read operations contain one or two bytes. The command code or register address
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determines the number of bytes to be read or written, See the register map for more information. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed (i.e. command code), and then data can be written to that register or read from it. The first byte of a read or write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. This write byte operation is shown in Figure 12. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. 2. The read byte operation is shown in Figure 13. First the command code needs to be written to the ADP4000 so that the required data is sent back. This is done by performing a write to the ADP4000 as before, but only the data byte containing the register address is sent, because no data is written to the register. A repeated start is then issued and a read operation is then performed consisting of the serial bus address; R/W bit set to 1, followed by the data byte read from the data register. 3. It is not possible to read or write a data byte from a data register without first writing to the address pointer register, even if the address pointer register is already at the correct value. 4. In addition to supporting the send byte, the ADP4000 also supports the read byte, write byte, read word and write word protocols.
1 SCL
9
1
9
SDA START BY MASTER
1
10
0
0
A1
A0
R/W ACK. BY ADP4000
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADP4000 STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 COMMAND CODE
Figure 11. Send Byte
1 SCL
9
1
9
SDA START BY MASTER
1
1
0
0
0
A1
A0
R/W ACK. BY ADP4000
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADP4000
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 COMMAND CODE 1 9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADP4000 STOP BY MASTER
FRAME 3 D ATA BYTE
Figure 12. Write Byte
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1 SCL 9 1 9
SDA START BY MASTER
1
10
0
0
A1
A0
R/W ACK. BY ADP4000
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT4000
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 COMMAND CODE
1 SCL
9
1
9
SDA
1
1
0
0
0
A1
A0
R/W ACK. BY ADP4000
D7
D6
D5
D4
D3
D2
D1
D0 NO ACK. BY MASTER STOP BY MASTER
REPEATED START BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE FROM ADP4000
Figure 13. Read Byte Write Operations
The PMBus specification defines several protocols for different types of read and write operations. The ones used in the ADP4000 are discussed in this section. The following abbreviations are used in the diagrams: S-START P-STOP R-READ W-WRITE A-ACKNOWLEDGE -NO ACKNOWLEDGE AThe ADP4000 uses the following PMBus write protocols.
Send Byte
out a single byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a single command byte to a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. For the ADP4000, the send byte protocol is used to clear Faults. This operation is shown in Figure 14.
1 2 3 4 COMMAND CODE 56 AP
In this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master asserts a stop condition on SDA and the transaction ends. The byte write operation is shown in Figure 15.
1 2 3 4 COMMAND CODE 5 6 7 8
SLAVE S WA ADDRESS
A DATA A P
Figure 15. Single Byte Write to a Register Write Word
SLAVE S WA ADDRESS
Figure 14. Send Byte Command
If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ACK and carry
In this operation, the master device sends a command byte and two data bytes to the slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends the first data byte. 7. The slave asserts ACK on SDA.
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ADP4000
8. The master sends the second data byte. 9. The slave asserts ACK on SDA. 10. The master asserts a stop condition on SDA and the transaction ends. The word write operation is shown in Figure 16.
1 2 3 4 COMMAND CODE 5 6 7 8 9 10 SLAVE S WA ADDRESS DATA DATA A A AP (LSB) (MSB)
7. The master sends the 7 bit slave address followed by the read bit (high). 8. The slave asserts ACK on SDA. 9. The slave sends the Data Byte. 10. The master asserts NO ACK on SDA. 11. The master asserts a stop condition on SDA and the transaction ends.
1 2 3 4 COMMAND CODE 5 6 7 8 9 10 11 P SLAVE S WA ADDRESS SLAVE AS R A DATA A ADDRESS
Figure 16. Single Word Write to a Register Block Write
In this operation, the master device sends a command byte and a byte count followed by the stated number of data bytes to the slave device as follows: 1. The master device asserts a START condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends the byte count N. 7. The slave asserts ACK on SDA. 8. The master sends the first data byte. 9. The slave asserts ACK on SDA. 10. The master sends the second data byte. 11. The slave asserts ACK on SDA. 12. The master sends the remainder of the data byes. 13. The slave asserts an ACK on SDA after each data byte. 14. After the last data byte the master asserts a STOP condition on SDA.
1 2 3 4 COMMAND CODE 11 A 5 A 6 7 8 9
Figure 18. Single Read from a Register Read Word
In this operation, the master device receives two data bytes from a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserted ACK on SDA. 6. The master sends a repeated start condition on SDA. 7. The master sends the 7 bit slave address followed by the read bit (high). 8. The slave asserts ACK on SDA. 9. The slave sends the first Data Byte (low Data Byte). 10. The master asserts ACK on SDA. 11. The slave sends the second Data Byte (high Data Byte). 12. The masters asserts a No ACK on SDA. 13. The master asserts a stop condition on SDA and the transaction ends.
1 2 3 4 COMMAND CODE 5 6 7 8 9 10 SLAVE S WA ADDRESS SLAVE DATA AS RA A ADDRESS (LSB) 11 12 13
SLAVE S WA ADDRESS 10
BYTE COUNT A =N 12 DATA BYTE N 13 A 14 P
DATA A BYTE 1
DATA BYTE 2
... ...
DATA AP (MSB)
Figure 17. Block Write to a Register Read Operations Figure 19. Word Read from a Command Code Block Read
The ADP4000 uses the following PMBus read protocols.
Read Byte
In this operation, the master device receives a single byte from a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserted ACK on SDA. 6. The master sends a repeated start condition on SDA.
In this operation, the master device sends a command byte, the slave sends a byte count followed by the stated number of data bytes to the master device as follows: 1. The master device asserts a START condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a REPEATED START condition on SDA.
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ADP4000
5. The master sends the 7-bit slave address followed by the read bit (high). 6. The slave asserts ACK on SDA 7. The slave sends the byte count N. 8. The master asserts ACK on SDA. 9. The slave sends the first data byte 10. The master asserts ACK on SDA. 11. The slave sends the remainder of the data byes, the master asserts an ACK on SDA after each data byte. 12. After the last data byte the master asserts a No ACK on SDA. 13. The master asserts a STOP condition on SDA.
1 2 3 4 5 6 7 SLAVE SLAVE BYTE COUNT S WAS RA ADDRESS ADDRESS =N 8 A 9 DATA BYTE 1 10 A 11 12 13 AP
Operation Command
The operation command, when enabled in the ON_OFF_Config command, can be used to start and stop the ADP4000 switching. The options available described in the Operation Command (0x01) in Table 11. There are two options for turning off, soft off and immediate off. There are three options for turning on. The first is ON, where the output voltage is soft started towards the Boot Voltage and then to the VID Voltage (same startup sequence as toggling EN). The other two options are margin high and margin low. When these options are selected the output voltage will settle on the VOUT_MARGIN_HIGH VID Code (0x25) or the VOUT_MARGIN_LOW VID Code (0x26).
Limits, ALERTs, and FAULTs
...
DATA BYTE N
Figure 20. Block Write to a Command Coder PMBus Timeout
The ADP4000 includes an PMBus timeout feature. If there is no PMBus activity for 35 ms, the ADP4000 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the PMBus expecting data. Some PMBus controllers cannot handle the PMBus timeout feature, so it can be disabled.
Configuration Register 1 (0xTBD)
Bit 3 SMB_TO_EN = 1; PMBus timeout enabled. Bit 3 TODIS = 0; PMBus timeout disabled (default).
Virus Protection
To prevent rogue programs or viruses from accessing critical ADP4000 register settings, the lock bit can be set. Setting Bit 0 of the Lock/Reset sets the lock bit and locks critical registers. In this mode, certain registers can no longer be written to until the ADP4000 is powered down and powered up again. For more information on which registers are locked see the register map.
ON_OFF_Config Command
The PMBus specifies an ON_OFF_Config which allows the user to configure when the ADP4000 should start and stop switching. There two control inputs, the EN input (specified as per VR11.1) and the Operation Command. The user can program the ADP4000 to respond to or ignore each of the control inputs. The default configuration is the EN pin is acted on, and the Operation Command is ignored. The EN pin is active high by default but can be programmed to be active low over PMBus. The details of the individual bits can be found in the description for Command Code 0x02 (ON_OFF_Config) in Table 11.
The ADP4000 monitors a number of voltage rails, temperatures, current etc. For each of the measured values there are ALERT and FAULT limits. When an ALERT or FAULT limit is exceeded then the ALERT or FAULT pin is asserted low and will remain low until the PMBus master does a Clear_Faults command and the measured value is back within the programmed limits. Take for example the temperature measurement Read_Temperature1 (0x8D). This value is compared with the OT_WARN_LIMIT (0x51) and the UT_WARN_LIMIT (0x52). If the measured temperature goes above the OT_WARN_LIMIT or under the UT_WARN_LIMIT then the corresponding Status bit is set Status_Temperature Command (0x7D) and an ALERT pin is pulled low. The ALERT pin will remain low until the PMBus master does a Clear_Faults command (0x03) and the measured temperature is back within the programmed limits. If the measured temperature exceeds the OT_FAULT_LIMIT (0x51) then Bit 7 of the Status_Temperature command gets set and the FAULT pin is asserted low. The intention is that a FAULT condition is worse than an ALERT condition. Each measured value is compared with appropriate high and low limits and the results of these comparisons are stored in Status Registers. See details of the various status registers in Table 11, commands 0x78, STATUS BYTE to 0x80 STATUS ALERT. The ADP4000 also allows the user to program which measured values can generate an ALERT and a FAULT using the Mask ALERT (0xF9) and Mask FAULT (0xFA) Commands. If the Mask VOUT Bit (Bit 7 is set in the Mask ALERT command) then the measured Vout going outside the programmed limits will set the appropriate Status bit but will not assert ALERT pin low. See command codes 0xF9 and 0xFA in Table 11 for more details.
Linear Mode
PMBus specifies two data format used for reporting back voltage, current and temperatures etc and for programming
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ADP4000
Limits. The ADP4000 uses Linear Mode. Linear Mode can be decoded as follows: X = Y*2^N Where X = the value (for example if this is current then it would be Amps, Temperature it would be C etc). The register readback is 16 Bits, the 5 MSB's are the Exponent (=N) and the 11 LSB's are the mantissa (=Y). Both the mantissa and exponent are 2's compliment values, if the MSB are 1 then they are negative values.
IOUT_CAL_GAIN and IOUT_CAL_OFFSET
the PMBus spec says this register should read back Amps. Therefore the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands need to be programmed to convert the Imon voltage into current in Amps. The following equation is used: READ_IOUT = Imon Voltage x IOUT_CAL_GAIN
+ IOUT_CAL_OFFSET
(eq. 19)
The IOUT_CAL_GAIN defaults to 1 and IOUT_CAL_OFFSET defaults to 0 which means the Imon voltage is stored in the READ_IOUT Command.
The ADP4000 measures the voltage on the Imon pin and stores that in the READ_IOUT Command (0x8C). However
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ADP4000
VR11 VID CODES for the ADP4000
OUTPUT OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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ADP4000
VR11 VID CODES for the ADP4000
OUTPUT 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 VID2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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ADP4000
VR11 VID CODES for the ADP4000
OUTPUT 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 VID7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID4 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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ADP4000
VR11 VID CODES for the ADP4000
OUTPUT 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 OFF OFF VID7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1
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ADP4000
Table 11. PMBus Commands for the ADP4000
Cmd Code 0x01 R/W R/W Default 0x80 Description Operation # Byte 1 Comment 00xx xxxx - Immediate Off 01xx xxxx - Soft Off 1000 xxxx - On (slew rate set by soft--start) - Default 1001 10xx - Margin Low (Act on Fault) 1010 10xx - Margin High (Act on Fault) Configures how the controller is turned on and off Bit 7:5 4 Default 1 0 Comment Reserved for Future Use This bit is read only. Switching starts when commanded by the Control Pin and the Operation Command, as set in Bits 3:0 0: Unit ignores OPERATION commands over the PMBus 1: Unit responds to OPERATION command, powerup may also depend upon Control input, as described in Bit 2 0: Unit ignores EN pin 1: Unit responds EN pin, powerup may also depend upon the Operation Register, as described for Bit 3 Control Pin Polarity 0 = Active Low 1 = Active High This bit is read only. 1 means that when the controller is disabled it will either immediately turn off or soft off (as set in the Operation Command)
0x02
R/W
0x17
ON_OFF_Config
1
3
1
2
1
1
1
0
1
0x03
W
NA
Clear_Faults
0
Writing any value to this command code will clear all Status Bits immediately. The SMBus ALERT is deasserted on this command. If the fault is still present the fault bit shall immediately be asserted again. The Write_Protect command is used to control writing to the PMBus device. There is also a lock bit in the Manufacture Specific Registers that once set will disable writes to all commands until the power to the ADP4000 is cycled. Data Byte 1000 0000 0100 0000 Comment Disables all writes except to the Write_Protect Command Disables all writes except to the Write_Protect and Operation Commands Disables all writes except to the Write_Protect, Operation, ON_OFF_Config and VOUT_COMMAND Commands Enables writes to all commands Disables all writes except to WRITE_PROTECT, PAGE and all MFR-SPECIFIC Commands
0x10
R/W
0x00
Write Protect
1
0010 0000
0000 0000 0001 0000
0x19
R
0xB0
Capability
1
This command allows the host to get some information on the PMBus device. Bit 7 6:5 Default 1 01 Comment PEC (Packet Error Checking is supported). Max supported bus speed is 400 kHz.
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ADP4000
Cmd Code R/W Default Description # Byte 4 3:0 0x20 0x21 0x25 0x26 0x38 0x39 0x4A R R/W R/W R/W R/W R/W R/W 0x20 0x00 0x0020 0x00B2 0x0001 0x0000 0x0064 VOUT_MODE VOUT_COMMAND VOUT_MARGIN_ HIGH VOUT_MARGIN_ LOW IOUT_CAL_GAIN IOUT_CAL_OFFSET IOUT_OC_WARN_ LIMIT 1 2 2 2 2 2 2 1 000 Comment ADP4000 has an SMBus ALERT pin and ARA is supported. Reserved
The ADP4000 supports VID mode for programming the output voltage. Sets the output voltage using VID. Sets the output voltage when operation command is set to Margin High. Programmed in VID Mode. Sets the output voltage when operation command is set to Margin Low. Programmed in VID Mode. Sets the ratio of voltage sensed to current output. Scale is Linear and is expressed in 1/ This offset is used to null out any offsets in the output current sensing circuitry. Programmed in Linear mode and units are Amps. This sets the high current--limit. Once this limit is exceeded IOUT_OC_WARN_LIMIT bit is set in the Status_IOUT register and an ALERT is generated. This limit is set in Amps and programmed in Linear Mode. This sets the temperature limit above which the Over Temp Fault Bit gets set in the Status_TEMPERATURE Register and the FAULT Output gets asserted. This limit is set using Linear Mode in C. This sets the temperature limit above which the Over Temp Warn Bit gets set in the Status_TEMPERATURE Register and the ALERT Output gets asserted. This limit is set using Linear Mode in C. This sets the temperature limit below which the Under Temp Warn Bit gets set in the Status_TEMPERATURE Register and the ALERT Output gets asserted. This limit is set using Linear Mode in C. This sets the input over voltage fault limit. Once exceeded the VIN Overvoltage Fault Bit, Bit 7, gets set in the Status Input Register and the FAULT output is asserted. This limit is set using Linear Mode, in V. This sets the input over voltage warn limit. Once exceeded the VIN Overvoltage Warn Bit, Bit 6, gets set in the Status Input Register and the ALERT output is asserted. This limit is set using Linear Mode, in V. This sets the input under voltage warn limit. Once exceeded the VIN Undervoltage Warn Bit, Bit 5, gets set in the Status Input Register and the ALERT output is asserted. This limit is set using Linear Mode, in V. This sets the output power over power fault limit. Once exceeded Bit 1 of the Status IOUT Command gets set and the FAULT output gets asserted (if not masked). This limit is set using Linear Mode in W. This sets the output power over power warn limit. Once exceeded Bit 0 of the Status IOUT Command gets set and the ALERT output gets asserted (if not masked). This limit is set using Linear Mode in W. Bit 7 Name BUSY Comment A fault was declared because the ADP4000 was busy and unable to respond. This bit is set whenever the ADP4000 is not switching. This bit gets set whenever the ADP4000 goes into OVP mode. This bit gets set whenever the ADP4000 latches off due to an over current event. This bit gets set when the input voltage falls below its programmed FAULT limit. This bit gets set when the Temperature, as measured using the THERMISTOR, exceeds its THERM and/or high or low limits.
0x4F
R/W
0x0055
OT_FAULT_LIMIT
2
0x51
R/W
0x0046
OT_WARN_LIMIT
2
0x52
R/W
0x0000
UT_WARN_LIMIT
2
0x55
R/W
0x0010
VIN_OV_FAULT LIMIT
2
0x57
R/W
0x0010
VIN_OV_WARN LIMIT
2
0x58
R/W
0x0000
VIN_UV_WARN LIMIT
2
0x68
R/W
0x012C
POUT_OP_ FAULT LIMIT POUT_OP_ WARN LIMIT STATUS BYTE
2
0x6A
R/W
0x012C
2
0x78
R
0x00
1
6 5 4
OFF VOUT_OV IOUT_OC
3
VIN_UV
2
TEMP
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ADP4000
Cmd Code R/W Default Description # Byte 1 0 0x79 R 0x0000 STATUS WORD 2 Byte Low Low Low Low CML None of the Above Bit 7 6 5 4 Name Res OFF VOUT _OV IOUT _OC Res TEMP Reserved This bit is set whenever the ADP4000 is not switching. This bit gets set whenever the ADP4000 goes into OVP mode. This bit gets set whenever the ADP4000 latches off due to an over current event. Reserved This bit gets set when the Temperature, as measured using the THERMISTOR, exceeds its THERM and/or high or low limits. A Communications, memory or logic fault has occurred. A fault has occurred which is not one of the above. This bit gets set whenever the measured output voltage goes outside its power good limits or an OVP event has taken place, i.e. any bit in Status VOUT is set. This bit gets set whenever the measured output current or power exceeds its warning limit or goes into OCP. i.e. any bit in Status IOUT is set. This bit gets set if the input voltage, as measured on VSENSE1 goes outside its programmed limits. i.e. any bit in Status VINPUT is set. A manufacturer specific warning or fault has occurred. The Power--Good signal is deasserted. Same as Power--Good in General Status. Reserved A Status bit in Status Other is asserted. Reserved Description This bit gets set whenever an OVP Event takes place. This bit gets set whenever the measured output voltage goes above its Power--Good limit. This bit gets set whenever the measured output voltage goes below its Power--Good limit. Not applicable. Comment A Communications, memory or logic fault has occurred. A fault has occurred which is not one of the above. Description
Low Low
3 2
Low Low High
1 6 7
CML None of the Above VOUT
High
6
Iout/Pout
High
5
INPUT
High High
4 3
MFR POWER _GOOD Res OTHER Res Name
High High High 0x7A R 0x00 STATUS VOUT 1 Bit 7
2 1 0
VOUT_ OVERVOLTAGE FAULT VOUT_ OVERVOLTAGE WARNING VOUT_ UNDERVOLTAGE WARNING VOUT_ UNDERVOLTAGE FAULT
6
5
4
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ADP4000
Cmd Code R/W Default Description # Byte 3 VOUT_MAX Warning TON_MAX_FAULT TOFF_MAX_ WARNING VOUT_TRACKING_ ERROR Name IOUT Overcurrent Fault Reserved IOUT Overcurrent Warning Reserved Reserved Reserved POUT Over--Power Fault POUT Over--Power Warning Name VIN Overvoltage FAULT VIN Overvoltage Warning Undervoltage Warning Reserved Reserved Reserved Reserved Reserved Name Overtemperature FAULT Comment Not supported, Can't program an output greater than max VID as there are no bits to program it. Not supported. Not supported. Not supported. Description This bit gets set if the ADP4000 latches off due to an OCP Event. Reserved This bit gets set if IOUT exceeds its programmed high warning limit. Reserved Reserved Reserved This bit gets set if the measured POUT exceeds the FAULT Limit. This bit gets set if the measured POUT exceeds the Warn Limit. Description This bit gets set when the input voltage goes above its programmed FAULT limit. This bit gets set when the input voltage goes above its programmed high limit. This bit gets set when the input voltage falls below its programmed low limit. Reserved Reserved Reserved Reserved Reserved Description This bit gets asserted when the temperature measured by the Thermistor connected to TTSENSE exceeds its THERM/FAULT Limit. This bit gets asserted when the temperature measured by the Thermistor connected to TTSENSE exceeds its High Temperature Limit. This bit gets asserted when the temperature measured by the Thermistor connected to TTSENSE exceeds its Low Temperature Limit. Reserved Reserved Reserved Reserved Reserved
2 1 0 0x7B R 0x00 STATUS IOUT 1 Bit 7 6 5 4 3 2 1 0 0x7C R 0x00 STATUS INPUT 1 Bit 7
6
5
4 3 2 1 0 0x7D R 0x00 STATUS_ TEMPERATURE 1 Bit 7
6
Overtemperature Warrning
5
Undertemperature Warrning
4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved
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ADP4000
Cmd Code 0x7E R/W R Default 0x00 Description STATUS CML # Byte 1 Bit 7 Name Invalid or Unsupported Command Received Invalid or Unsupported Data Received PEC Failed Memory Fault Detected Processor Fault Detected Reserved A communication fault other than the ones listed has occurred. Other memory or Logic Fault has occurred. Name Reserved Reserved VSENSE2 FAULT Reserved Reserved Gets asserted when VSENSE2 exceeds it programmed FAULT limits. Gets asserted when VSENSE2 exceeds it programmed OV WARN limits. Gets asserted when VSENSE2 exceeds it programmed UV WARN limits. Gets asserted when VSENSE2 exceeds it programmed WARN limits. Gets asserted when VSENSE2 exceeds it programmed FAULT limits. Reserved Supported Comment Description
6
Supported
5 4 3 2 1
Supported Not Supported Not Supported Reserved Supported
0
Not Supported
0x80
R
0x00
STATUS_ALERT
1
Bit 7 6 5
Description
4
VSENSE2 OV WARN VSENSE2 OV WARN VMON WARN
3
2
1
VMON FAULT
0 0x88 0x8B 0x8C 0x8D R R R R 0x00 0x00 0x00 0x00 READ_VIN READ_VOUT READ_IOUT READ_ TEMPERATURE1 READ_POUT MFR_ID MFR_MODEL MFR_REVISION 2 2 2 2
Reserved
Readback input voltage (measured using VSENSE1). Voltage is read back in Linear Mode Readback output voltage. Voltage is read back in VID Mode. Readback output current. Current is read back in Linear Mode (Amps). Readback temperature 1. Thermistor, connected to TTSENSE is the sense element. Temperature is read back in Linear Mode C. Readback Output Power, read back in Linear Mode in W's. 0x41 0x4000 0 Readback using the Block command with the Byte count equal to 1. Readback using the Block command with the Byte count equal to 2. Readback using the Block command with the Byte count equal to 1.
0x96 0x99 0x9A 0x9B
R R R R
0x00 0x41 0x4000 0x01
2 1 2 1
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ADP4000
Table 12. Manufacturer Specific Command Codes for the ADP4000
Cmd Code 0xD0 R/W R/W Default 0x00 Description Lock/Reset # Byte 1 Bit 1 0 Name Reset Lock Comment Description Resets all registers to their POR Value. Has no effect if Lock bit is set. Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read-only and cannot be modified until the ADP4000 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings (Lockable). Description These bits sets the number of phases turned on during PSI. 00 = 1 Phase enabled during PSI 01 = 2 Phases enabled during PSI 10 = 3 Phases enabled during PSI 11 = 1 Phase enabled during PSI Reserved Reserved PMBus Timeout Enable. When the PMB_TO_EN bit is set to 1, the PMBus Timeout feature is enabled. In this state if, at any point during an PMBus transaction involving the ADP4000, activity ceases for more than 35 ms, the ADP4000 assumes the bus is locked and releases the bus. This allows the ADP4000 to be used with SMBus controllers that cannot handle SMBus timeouts (Lockable). Enable the FAULT pin, Default = 1 Enable the ALERT pin When the ENABLE_MONITOR bit is set to 1, the ADP4000 starts conversions with the ADC and monitors the voltages and temperatures. Description 000 = Phase 1 001 = Phase 2 010 = Phase 3 011 = Phase 4 100 = Phase 5 101 = Phase 6 All other codes = Phase 6 When the VID_EN bit is set to 1, the VID code in the VOUT_COMMAND register sets the output voltage. When VID_EN is set to 0, the output voltage follows the VID input pins. When the LOOP_EN bit is set to 1 in both registers, the control loop test function is enabled. This allows measurement of the control loop AC gain and phase response with appropriate instrumentation. The control loop signal insertion pin is IMON. The control loop output pin is COMP.
0xD1
R/W
0x07
Mfr Config
1
Bit 7:6
Name PSI
5 4 3
Reserved Reserved PMB_TO_EN
2 1 0
FAULT_EN ALERT_EN ENABLE_ MONITOR
0xD2
R/W
0x52
VR Config 1A
1
Bit 6:4
Name Phase Enable Bits
3
VID_EN
2
LOOP_EN
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ADP4000
Cmd Code R/W Default Description # Byte 1 CLIM_EN Comment When CLIM_EN is set to 1, the current--limit time out latchoff functions normally. When this bit is set to 0 in both registers, the current--limit latchoff is disabled. In this state, the part can be in current--limit indefinitely. Reserved
0 0xD3 R/W 0x52 VR Config 1B 1
Reserved
This register is for security reasons. It has the same format as register 0xD2. Bits need to be set in both registers for the function to take effect. This resister sets TD1, TD3 and TD5 delays for the soft--start sequence. The current--limit latchoff timer is 4 times the programmed delay time. 000 = 0.5 ms 001 = 1 ms 010 = 1.5 ms 011 = 2 ms = default 100 = 2.5 ms 101 = 3 ms 110 = 3.5 ms 111 = 4 ms This register sets the soft--start voltage slew rate, and hence TD2 and TD4, of the soft--start sequence. 000 = 0.1 V/ms 001 = 0.3 V/ms 010 = 0.5 V/ms = default 011 = 0.7 V/ms 100 = 0.9 V/ms 101 = 1.1 V/ms 110 = 1.3 V/ms 111 = 1.5 V/ms This register sets the slew rate during a dynamic VID. 000 = 1 V/ms 001 = 3 V/ms = default 010 = 5 V/ms 011 = 7 V/ms 100 = 9 V/ms 101 = 11 V/ms 110 = 13 V/ms 111 = 15 V/ms This is a 16 bit value that reports back the voltage on the VSENSE2 Pin. Can be configured to measure the input Voltage Current. 16 Bit Value between 0 and 2.0 V. Voltage is reported using Linear Mode. This is a 16 bit value that reports back the voltage on the VTT Pin. Voltage is reported using Linear Mode. This is a 16 bit value that reports back the voltage measured between FB and FBRTN. Voltage is reported using Linear Mode. Offset Command Code for VOUT, max 200 mV. Offset Command Code for VOUT, max 200 mV. This value sets the internal load line attenuation DAC calibration value. The maximum load line is controlled externally by setting the gain of the current sense amplifier as explained in the applications section. This maximum load line can then be adjusted from 100% to 0% in 30 steps. Each LSB represents a 3.33% change in the load line. 00000 = No Load Line 10000 = 50% of external load line 11111 = 100% of external Load Line This value sets the internal load line attenuation DAC value. The maximum load line is controlled externally by setting the gain of the current sense amplifier as explained in the applications section. This maximum load line can then be adjusted from 100% to 0% in 30 steps. Each LSB represents a 3.33% change in the load line. 00000 = No Load Line 10000 = 50% of external load line 11111 = 100% of external Load Line
0xD4
R/W
0x03
Ton Delay
1
0xD5
R/W
0x02
Ton Rise
1
0xD6
R/W
0x01
Ton Transition
1
0xD7
R
0x00
VSENSE2 Voltage
2
0xD8 0xDA 0xDB 0xDC 0xDE
R R R/W R/W R/W
0x00 0x00 0x00 0x00 0x10
EN/VTT Voltage VMON Voltage VOUT_TRIM VOUT_CAL Load Line Calibration
2 2 1 1 1
0xDF
R/W
0x00
Load Line Set
1
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34
ADP4000
Cmd Code 0xE0 R/W R/W Default 0x00 Description PWRGD Hi Threshold # Byte 1 Comment This value sets the PWRGD Hi Threshold and the CROWBAR Threshold: Code = 00, PWRGD HI = 300 mV (default) Code = 01, PWRGD HI = 250 mV Code = 10, PWRGD HI = 200 mV Code = 11, PWRGD HI = 150 mV This value sets the PWRGD Lo Threshold: Code = 000, PWRGD Lo = -500 mV (default) Code = 001, PWRGD Lo = -450 mV Code = 010, PWRGD Lo = -400 mV Code = 011, PWRGD Lo = -350 mV Code = 100, PWRGD Lo = -300 mV Code = 101, PWRGD Lo = -250 mV Code = 110, PWRGD Lo = -200 mV Code = 111, PWRGD Lo = -150 mV This value sets the internal current--limit adjust value. The default current--limit is programmed using a resistor to ground on the LIMIT pin. The value of this register adjusts this value by a percentage between 50% and 146.7%. Each LSB represents a 3.33% change in the threshold. 11111 = 146.7% of external current--limit 10000 = 100% of external current--limit (default) 00000 = 50% of external current--limit These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by 25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by 25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by 25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by 25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by 25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 These values adjust the gain of the internal phase balance amplifiers. The nominal gain is set to 5. These registers can adjust the gain by 25% from 3.75 to 6.25. Code = 00000, Gain of 3.75 Code = 10000, Gain of 5 (default) Code = 11111, Gain of 6.25 This is the temperature below which the VTHOT will de--assert. VSENSE2 voltage high limit. VSENSE2 voltage low limit. VSENSE2 voltage FAULT limit. VMON FAULT Limit.
0xE1
R/W
0x00
PWRGD Lo Threshold
1
0xE2
R/W
0x10
Current--Limit Threshold
1
0xE3
R/W
0x10
Phase Bal SW1
1
0xE4
R/W
0x10
Phase Bal SW2
1
0xE5
R/W
0x10
Phase Bal SW3
1
0xE6
R/W
0x10
Phase Bal SW4
1
0xE7
R/W
0x10
Phase Bal SW5
1
0xE8
R/W
0x10
Phase Bal SW6
1
0xEE 0xEF 0xF0 0xF1 0xF5
R/W R/W R/W R/W R/W
0x0050 0x0002 0x0000 0x0002 0x0002
VRHOT RESET LIMIT VSENSE2 High Limit VSENSE2 Low Limit VSENSE2 FAULT Limit VMON FAULT Limit
2 2 2 2 2
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ADP4000
Cmd Code 0xF6 0xF7 0xF8 0xF9 R/W R/W R/W R/W R/W Default 0x0002 0x07CE 0x007B 0x00 Description VMON Warn Limit TTSENSE Gain TTSENSE Offset Mask ALERT # Byte 2 2 2 1 VMON Warn Limit. Gain information used to convert TTSENSE Voltage to temperature. Offset information used to convert TTSENSE Voltage to temperature. Bit 7 6 5 4 3 2 1 0 0xFA R/W 0x00 Mask FAULT 1 Bit 7 6 5 4 3 2 1 0 0xFB R/W 0x00 General Status 1 Bit 7 6 5 4 0xFC R 0x00 Phase Status 1 Bit 7 6 5 4 3 Name Mask VOUT Mask IOUT Mask Input Mask Temperature Mask CML VMON VSENSE2 Mask POUT Name Mask VOUT Mask IOUT Mask Input Mask Temperature Mask CML VMON VSENSE2 Mask POUT Name FAULT ALERT POWER--GOOD RDY Name Phase 6 Phase 5 Phase 4 Phase 3 Phase 2 Description This bit is set to 1 when Phase 6 is enabled. This bit is set to 1 when Phase 5 is enabled. This bit is set to 1 when Phase 4 is enabled. This bit is set to 1 when Phase 3 is enabled. This bit is set to 1 when Phase 2 is enabled. Replaced by Bit 3 of the Status Word Command. Description Masks any ALERT caused by bits in Status VOUT Register. Masks any ALERT caused by bits in Status IOUT Register. Masks any ALERT caused by bits in Status Input Register. Masks any ALERT caused by bits in Status Temperature Register. Masks any ALERT caused by bits in Status CML Register. Masks any ALERT caused by VMON exceeding its high or low limit. Masks any ALERT caused by VSENSE2 exceeding its high or low limit. Masks any ALERT caused by POUT exceeding its programmed limit. Description Masks any FAULT caused by bits in Status VOUT Register. Masks any FAULT caused by bits in Status IOUT Register. Masks any FAULT caused by bits in Status Input Register. Masks any FAULT caused by bits in Status Temperature Register. Masks any FAULT caused by bits in Status CML Register. Masks any FAULT caused by VMON exceeding its high or low limit. Masks any FAULT caused by VSENSE2 exceeding its high or low limit. Masks any FAULT caused by POUT exceeding its programmed limit. Description Comment
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ADP4000
PACKAGE DIMENSIONS
LFCSP48 7x7, 0.5P CASE 932AD--01 ISSUE O
D D1
PIN ONE REFERENCE
A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D1 D2 E E1 E2 e H K L M MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 7.00 BSC 6.75 BSC 4.95 5.25 7.00 BSC 6.75 BSC 4.95 5.25 0.50 BSC -----12 0.25 -----0.30 0.50 -----0.60
E1
E
0.20 C 0.20 C TOP VIEW H 0.10 C
NOTE 4
(A3) A
0.08 C
SIDE VIEW
A1 C
SEATING PLANE
4X
M
13
D2
K
25
4X
M
SOLDERING FOOTPRINT*
7.30 5.14 0.63
48X
PIN 1 INDICATOR 1 48 37 48X
E2
48X
1 L
5.14
7.30
e BOTTOM VIEW
b 0.10 C A B 0.05 C
NOTE 3
PACKAGE OUTLINE
0.50 PITCH
0.28
DIMENSIONS: MILLIMETERS
48X
*For additional information on our Pb--Free strategy and solder details, please download the ON Semiconductor Soldering a Mounting Techniques Reference Manual, SOLDERRM/D.
FlexMode is a trademark of Analog Devices, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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ADP4000/D

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